Summary Of Tests
System RAM is tested in three stages: low 2 kbytes, middle (up to 64k), and from 64k to top. The test patterns used are: all Is, all Os, a counting pattern (data = low word of the address), reverse counting pattern (data = complement of address low word). The counting pattern is copied from the top and bottom of a 32 Kbyte buffer into the current 32 Kbytes of video RAM, then shifts video RAM to a new area, verifies the pattern, and repeats the test, until the top of RAM is reached. Finally, addressing at 64k boundaries is checked by writing unique pattern in last 256 bytes of each 64k block.
If an error occurs, the display turns red accompanied by an oscillating tone and the error code is displayed, followed by the address, data written, data read, and the bits which did not agree.
For example: " R2 45603E W:6Q3E R:613C bad bits: 1,8".
The address as well as the bit position must be used to find the correct RAM chip. The following table gives a correspondence between the addresses and banks:
|
Main PCB (First Megabyte): | |
|
Bad ftit(s) |
RAM Chip |
|
0-3 |
U500 |
|
4-7 |
U501 |
|
8-11 |
U502 |
|
12-15 |
U503 |
|
16-19 |
U504 |
|
20-23 |
U505 |
|
24-27 |
U506 |
|
28-31 |
U507 |
|
Main PCB (Second Megabyte): | |
Address
1Q0000-1FFFFF
Address
1Q0000-1FFFFF
|
Bad Bit(s) |
RAM Chip |
|
0-3 |
U508 |
|
4-7 |
U509 |
|
8-11 |
U510 |
|
12-15 |
U511 |
|
16-19 |
U512 |
|
20-23 |
U513 |
|
24-27 |
U514 |
|
28-31 |
U515 |
2/8 Megabyte ST RAM expansion Board:
|
LSR OF Address |
Rad Ritisï |
RAM Chip |
|
0 or B |
0-3 |
U17 |
|
4-7 |
U18 | |
|
8-11 |
U19 | |
|
12-15 |
U20 | |
|
2 or A |
0-3 |
U10 |
|
4-7 |
Uli | |
|
8-11 |
U14 | |
|
12-15 |
U15 | |
|
4 or C |
0-3 |
U5 |
|
4-7 |
U6 | |
|
8-11 |
U7 | |
|
12-15 |
U8 | |
|
6 or E |
0-3 |
U1 |
|
4-7 |
U2 | |
|
8-11 |
U3 | |
|
12-15 |
U4 | |
|
4/16 Megabyte T |
T RAM expansion Board | |
|
LSR OF Address |
Rad Ritisï |
RAM Chip |
|
0, 4, B, orC |
0-7 |
U104 |
|
8-15 |
U105 | |
8-15 U1Q3
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