Synchronous Bus interface
The ACIA uses the E Clock, which unfortunately the MC68SEC000 CPU doesn't provide. The E Clock was at one tenth of the CPU frequency with a 60/40 duty cycle.
The 68SEC000 also doesn't have connections for the VPA or VMA signals.
The E Clock was created by a counter that counts from 0 to 9 and then rolls over. If the value of the counter was 0 to 5 then the E clock was 0, otherwise it will be 1. The Glue component of the Atari
ST then asserts the VPA
signal to tell the CPU an access to a 6800 synchronous device has been made, which in the Atari ST was an access to the Keyboard or Midi ACIA MC6850. The VPA
signal was checked when the E Clock counter was 2, and if it was active then VMA was asserted. DTACK was then asserted later when the E Clock counter was 8 or 9 to end the bus cycle. By asserting DTACK late, the CPU automatically inserts wait states. Appendix E shows the Clock VHDL component.
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