Segment Display
As part of debugging, a VHDL component was created to use the RaggedStone onboard 7 segment display. The RaggedStone has four of these 7 segment displays, enabling 4 hex characters (or 16 bits) to be displayed. This was perfect for displaying the 16 bit data bus, but not the 24 bit address bus. To overcome this limitation, the display will sequence through the upper portion of the address bus, then the lower portion of the address bus and lastly the data bus.
The VHDL component will also be responsible for changing the 4 bit hex value into a value to drive the 7 segment display. The 7 segment displays on the RaggedStone, are just a set of LEDs with no intelligence. Another part it will cater for was scanning the digits of the 7 segment display. Only one digit can be displayed at one time, and thus it needs to scan through the digits quick enough for the human eye not to see any flicker. Appendix G shows this VHDL component. One problem encountered was that the mapping for the digits to FPGA pins listed in the RaggedStone user manual appears to be wrong. The table below shows the correct pin mapping.
|
Digit 1 |
Digit 2 |
Digit 3 |
Digit 5 |
|
FPGA U14 |
FPGA AA17 |
FPGA U17 |
FPGA U16 |
- Table 7 - FPGA connections for 7 segment display
Figure 25 - 7 segment display
Figure 25 - 7 segment display
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