Segment Display
As part of debugging, a VHDL component was created to use the RaggedStone onboard 7 segment display. The RaggedStone has four of these 7 segment displays, enabling 4 hex characters or 16 bits to be displayed. This was perfect for displaying the 16 bit data bus, but not the 24 bit address bus. To overcome this limitation, the display will sequence through the upper portion of the address bus, then the lower portion of the address bus and lastly the data bus. The VHDL component will also be...
Ide
Although there exists a simple IDE interface for the Atari ST that is compatible to the Atari Falcons IDE port, it only works in programmed I O mode. This is where the CPU has to do the work of moving the data to and from the IDE bus to RAM. Although this is fine for most small chunks of data, large files will inevitably tie up the CPU stopping it from doing more useful processing. A solution could exist in using the original DMA component with a bridge layer to IDE protocol. This would provide...
References
All online references sited 29th April 2008. 1 Old-Computers.com The Museam. Online . Available 2 Wikipedia. unknown . TV Boy. Online . Available http en.wikipedia.org wiki TV_Boy 3 Howard Wen. 2007 . Curt Vendel The Escapist Interview. Online . Available 4 Benjamin J Heckendorn. 2006 . Still looking for NES on a Chips . Online . Available 5 Rieks Warendorp Torringa Sander Zuidema. 2006 . Bazix Homepage. Online Available http www.bazix.nl 6 Dennis Van Weeren. 2008 . MiniMig Homepage. Online ....
Synchronous Bus interface
The ACIA uses the E Clock, which unfortunately the MC68SEC000 CPU doesn't provide. The E Clock was at one tenth of the CPU frequency with a 60 40 duty cycle. The 68SEC000 also doesn't have connections for the VPA or VMA signals. The E Clock was created by a counter that counts from 0 to 9 and then rolls over. If the value of the counter was 0 to 5 then the E clock was 0, otherwise it will be 1. The Glue component of the Atari signal to tell the CPU an access to a 6800 synchronous device has...
Noac
Another unlicensed reversed engineered copy of a console exists, based on Nintendo's NES Nintendo Entertainment System . These are known as NOAC Nintendo On A Chip and originate from a variety of manufactures in China and are inaccurate in many ways to an original NES 4 . The Integrated Circuit is supplied without a real physical package, instead being covered with an epoxy glue material. A brief look on the internet at current and past projects in this particular field has shown the following...
ACIA IP Core
At this stage the keyboard ACIA was added to the project. Interrupts are required for this component to work, so the relevant connections between the Glue which contains a simple interrupt priority encoder and the CPU IPL 2 0 signals are made. Only three of the CPU interrupt levels are used in the Atari ST as shown in the table below. The MFP acts as an additional cascaded interrupt controller. Now the ACIA was built into the project and an original Atari ST keyboard was connected, the keyboard...
Minimig
The Minimig short for Mini Amiga is based around a Xilinx FPGA and MC68SEC000 CPU. It has some key changes from the original Amiga 500, including support for a PS 2 mouse and keyboard and games that load from a removable MMC Flash memory device 6 . The source code for both the FPGA and PIC microcontroller became available to download on 24 07 2007 and the hardware is available to buy through online resellers. Figure 5 - Minimig PCB
Fpga
An FPGA is a programmable logic device, with the configuration being volatile. The FPGA contains many complex logic blocks that have interconnects running between them in a grid like fashion. There are also dedicated interconnects like global clock lines. The configuration is often programmed in a high level HDL Hardware descriptive Language like Verilog or VHDL, or sometimes as a schematic. The majority of modern FPGAs contain embedded functions, such as adders, multipliers, memory, digital...
DMA IP Core
At this point the DMA IP Core was added. The requirement for the DMA to take over and master the system bus required quite a large change to the way the components were connected together at the top level. Instead of just the CPU driving the control signals for bus cycles AS , R W , UDS and LDS the Glue also needs to be able to drive these signals. Even on a DMA bus cycle, it is the Glue that drives the control signals and does the bus arbitration with the CPU. The MMU also helps out by...
Software Over Scan
Although not deemed as necessary, using software that attempts to use the hardware in ways that were not specified by Atari is a good test of compatibility. Just like the special effects for the sound chip, as mentioned in paragraph 6.2 there were also techniques to gain special graphics. One of these is software over scanning. The Atari ST low resolution mode is 320 x 200 pixels, but in fact displays a lot Figure 47 - Screen borders more in the form of borders around the working screen area as...
Other differences between the original Atari ST and the design
The Atari ST as mentioned previously has 3 different resolutions. The monochrome high resolution has vertical and horizontal timings that are close to the VGA specification. The Low and Medium colour resolutions, which were designed to be displayed on a television, do not meet the VGA timing specification. The problem arises from the slow pixel clock, resulting in a horizontal synchronisation frequency of 15 KHz, which is half of VGA timing. To use the Atari ST in all three resolutions it meant...
MMU IP core
enable the system to run further through mounted onto the RaggedStones left hand I O bank. One of the MMUs tasks was to keep the Atari ST DRAM memory refreshed. As the design was using SRAM this refreshing must be disabled. This also makes debugging far easier as the only accesses to RAM will be memory accesses, not refresh cycles as well. To remove the refreshing the refresh address counter was removed from the multiplexer in wf25912ip_ram_adrmux. vhd. ADR when MCU PHASE RAM and DMAn '1 DMA...
VGA Colour pattern
The next step was to implement a Digital to Analogue Converter DAC for the Red, Green and Blue signals to drive the VGA port. The converter being used was an ST Microelectronics STV8438, which is capable of 3 x 8bit colour. As the Atari ST can only produce 3 x 4bit colour, the MSB Most Significant Bits are used and the rest are tied low. Appendix B shows the schematic. signal counter std_logic_vector 2 4 downto 0 To drive the VGA monitor a colour pattern generator was discovered written by...
YM IP Core
Next to implement was the Yamaha YM2149 sound generator. This IP core differs in the fact that the original semiconductor has an analogue output stage, but in a Xilinx Spartan FPGA and the vast majority of other FPGAs are not mixed signal. Instead the IP core uses a fast PWM Pulse Width Modulation and an external low pass discrete filter to create the 'shape'. In the implementation the 3 channels of sound are externally mixed with resistors and then into a simple RC low pass filter. The first...
Flashing LED
The first task was to make sure that the oscillator clock works and that the JTAG programming works. To do this a simple LED flash routine was written. However, before this was done, constraints for the I O pin mapping and a top level component needed to be written. This was done by looking at the schematics of the RaggedStone development board and laboriously assigning names for each I O pin. Appendix A lists the constraints file and component file. Shown right was the VHDL architecture for...
Benchmarking
Benchmarking software are useful tools to identify the performance of a computer. By running benchmark software on the system, it should be possible to identify any errors either in performance or functionality. The program used is called Gembench written by Ofir Gal in 1995, along with another program called SysInfo by Thorsten Bergner in 1997. Gembench benchmarks the AES opening dialog boxes, scrolling text etc , CPU speed maths routines and memory bandwidth. SysInfo reports information on...
Colour Palette
In the colour resolution modes the colours were incorrect compared to an Atari ST. At first the connection between the FPGA and Video DAC were checked and these were correct. The connections between the Video DAC and VGA connector were also correct. With the floppy drive now operational, it was possible to load programs in. An art drawing program called Degas Elite written by Tom Hudson in 1987 was loaded from the floppy drive. With this program it is possible to change the shade of colour in...
Glue IP core
Before trying the system the Glue VHDL IP Core had to be added. It was at this point that I noticed the IP Cores at the top level used bit and bit_vector signal types and all the other components that I had written used std_logic and std_logic_vector. It is possible to convert between the two types, but this can become untidy because it is no possible to do the conversion within the component port maps. A decision was made to alter the previous components to use bit and bit_vector which creates...
Clock
The clock component was necessary for generation of clock signals from the master clock, which in the Atari ST was 32 MHz. Below, was the clock frequencies that each component of the Atari ST needs. It was found that it's very important to use the dedicated DCM Digital Clock Management PLLs Phase Locked Loops that are provided inside the Xilinx Spartan. Using these reduces clock skew and jitter, and also use dedicated global clock routes inside the FPGA. This was to help prevent the clock edges...
IP Cores
IP Core stands for Intellectual Property Core. They are a block of logic as an element to design reuse, a trend towards repeated use of previously designed components. IP cores may be licensed to another party or can also be owned and used by a single party alone. Some cores are only offered as netlists, to protect the vendor against reverse-engineering. Others are offered as synthesizable cores in hardware descriptive languages like Verilog or VHDL 16 . There are already a couple of projects...
Writing bytes to Flash Memory
Next on the list was to load data into the RaggedStone onboard Flash memory. A design was found on the Xilinx website for the Spartan-3A 3AN Development Starter Kit. This design was intended to be used with the ST Microelectronics M29DW323DT Flash memory that was featured on the Xilinx Spartan-3A 3AN development board. It Figure 20 -Flash Programmer menu uses the Xilinx Picoblaze embedded PicoElaze H29DW323DT FLASH Programmer vl.00 E-Erase all B-Erase blocks 0-5 P-Pnogram HCS File B-Drite byte...
Base Hardware
The design is to be based around a Xilinx FPGAs, as there are special free versions of the IDE Integrated Development Environment which are only slightly limited from the commercial versions. The type of Xilinx fitted to the board needs to be large enough in terms of logic elements to fit the whole project, which is not something that can be estimated easily. The Atari ST is based on a 5 volt logic platform, and so having some 5 volt capabilities on the chosen development board will be a real...